Tag Mask Insert inserts the tag in the first source register into the excluded set specified in the second source register, writing the new excluded set to the destination register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | Xm | 0 | 0 | 0 | 1 | 0 | 1 | Xn | Xd | ||||||||||||
| sf | S | opcode | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_MTE) then UNDEFINED; integer d = UInt(Xd); integer n = UInt(Xn); integer m = UInt(Xm);
| <Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Xd" field. |
| <Xn|SP> |
Is the 64-bit name of the first source general-purpose register or stack pointer, encoded in the "Xn" field. |
| <Xm> |
Is the 64-bit name of the second general-purpose source register, encoded in the "Xm" field. |
bits(64) address = if n == 31 then SP[] else X[n, 64]; bits(64) mask = X[m, 64]; bits(4) tag = AArch64.AllocationTagFromAddress(address); mask<UInt(tag)> = '1'; X[d, 64] = mask;
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.